Implementation of AES encryption on real time data stream using FPGA (P-0374) (MFN 8525)

Abstract

In the modern world, digital communication is advancing in multitude of fields. The communication can be between two persons or among interrelated devices just like in the case of Internet of Things (IoT). As the attackers are becoming sophisticated day by day, there is a need to secure the data transmission. For that purpose, encryption is done (an art of cryptography). Then comes the choice whether to go for the software implementation of the encryption algorithm or the hardware implementation. The problem with the software implementation is that it is not fast enough and has long development cycle issues. Therefore, hardware implementation is preferred. But some encryption algorithms also have their limitations, therefore the data is not well protected. Since the year 2001 the accepted standard for data encryption according to NIST is AES(Advanced Encryption Standards). With AES-128, 268 bytes of data can be encrypted before running into a 50% chance of collision. That is why we have opted for AES-128 because of its higher degree of protection and larger block size. We have chosen FPGA because it gives more flexibility in terms of hardware designing since it is reconfigurable. This project addresses the need for secure data transmission among embedded systems. The AES- 128 encryption algorithm is implemented on Xilinx FPGA part from Spartan 3A family of devices. Counter mode (CTR) of operation is used through which optimized hardware is achieved and resource utilization kept to minimum. Data is acquired using a sync transmitter receiver. A Theoretical throughput of 14Mbps is achieved.