FPGA Implementation Of Present Cipher With Self-Test Ability

Abstract

Increased complexity of VLSI circuits has led to higher occurrences of faults in Integrated Circuit (IC). Moreover, testing of huge number of devices in loT technology is an important requirement from reliability point of view. Therefore a low-cost but efficient testing technique is required for deployment in loT environment where majority of the devices (and wireless sensor nodes) have limited resources in terms of power and hardware area. Scan chains and built-in self-test (BIST) techniques are two very popular self-test approaches that allow a device to test itself without requiring external testing equipment. Scan chain provides higher fault coverage but brings security risks. Unlike scan chains, BIST techniques are more secure as these do not provide access to internal device nodes. But all the implementation techniques of scan-chain and BIST usually requires extra internal components like linear feedback shift register (LFSR) and multiple input signature register (MISR) as test pattern generator (TPG) and signature analyzer (SA) respectively. These extra components result in higher area overhead and hence make them unsuitable for deployment in loT environment. This research work focuses on a compact hardware implementation of PRESENT cipher with self-test ability. The compactness of the proposed design is achieved due to inherent structure of PRESENT cipher and its utilization as self-test structure along with low cost components. The proposed design is coded in VHDL (VHSIC Hardware Description Language) and Linux ISE design suite is used for the simulation, synthesis and implementation on different Linux based FPGA platforms. A comprehensive performance analysis on the basis of the hardware area overhead, fault coverage and randomness of test patterns shows that the proposed self-test method is about 23% lighter than the LFSR and MISR based self-test test structures with the fault coverage of over 99%. From the results it can be concluded that the proposed self-test design is one of the most viable self-test structure in resource constraint environment as improvement ix in hardware area is achieved without any compromise on other important aspects such as fault coverage, throughput, power consumption and quality of the teat patterns.