Hardware implementation of forward error Correction (FEC) for machine type Communication (MTC) (T-0436) (MFN 8082)

Abstract

For 5G wireless system, three scenarios are identified by 3GPP and METIS project. The scenarios are Enhanced Mobile broadband (eMBB), Massive Machine Type communication (mMTC), and Ultra Reliable Low latency Communication (URLLC). In 5G wireless system the massive number of devices carries information in the form of short packets. Short packets are very prone to errors so URLLC scenario requires ultra reliable communication, for which efficient coding schemes are required. The coding scheme which has less complex and low hardware overhead is required. The polar codes using Successive Cancellation (SC) Decoding has the simplest and least complex hardware. The encoder and decoder are designed through resource sharing as much as possible. The encoder is designed using Shift Register based Partial Sum Unit (SR-PSU) method, in which parallel computation is performed. The decoder is designed using successive cancellation decoding method. The Processing Unit (PU) in the decoder hardware is designed and used once which reduces the area of implementation. The encoder and decoder are combined in the transceiver hardware through resource sharing and implemented on FPGA device Kintex7 (XC7K70T).