A high‐speed RSD‐based flexible ECC processor for arbitrary curves over general prime field

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dc.contributor.author Yasir Ali Shah
dc.contributor.author Khalid Javeed
dc.contributor.author Shoaib Azmat
dc.contributor.author Xiaojun Wang
dc.date.accessioned 2018-11-29T07:02:53Z
dc.date.available 2018-11-29T07:02:53Z
dc.date.issued 2018
dc.identifier.uri http://hdl.handle.net/123456789/7755
dc.description.abstract This workpresents a novel high‐speed redundant‐signed‐digit (RSD)‐based elliptic curve cryptographic (ECC) processor for arbitrary curves over a general prime field. The proposed ECC processor works for any value of the prime number and curve parameters. It is based on a new high speed Montgomery multiplier architecture which uses different parallel computation techniques at both circuit level and architectural level. At the circuit level, RSD and carry save techniques are adopted while pre‐computation logic is incorporated at the architectural level. As a result of these optimization strategies, the proposed Montgomery multiplier offers a significant reduction in computation time over the state‐of‐the‐art. At the system level, to further enhance the overall performance of the proposed ECC processor, Montgomery ladder algorithm with (X,Y)‐only common Z coordinate (co‐Z) arithmetic is adopted. The proposed ECC processor is synthesized and implemented on different Xilinx Virtex (V) FPGA families for field sizes of 256 to 521 bits. On V‐6 platform, it computes a single 256 to 521 bits scalar point multiplication operation in 0.65 to 2.6 ms which is up to 9 times speed‐up over the state‐of‐the‐art. en_US
dc.language.iso en en_US
dc.publisher Bahria University Islamabad Campus en_US
dc.relation.ispartofseries ;DOI: 10.1002/cta.2504
dc.subject Department of Computer Engineering en_US
dc.title A high‐speed RSD‐based flexible ECC processor for arbitrary curves over general prime field en_US
dc.type Article en_US


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