DEVELOPMENT OF 32-BITS MIPS ARCHITECTURE FOR FLOATING POINT ARITHMETIC

Abstract

DSP (Digital Signal Processing) is one of the most powerful technologies that will shape science and engineering in the twenty-first century. This encouraged us to explore DSP through MIPS processor. The major problem we came across is to synchronize 32 bit Floating Point Unit for addition, subtraction, multiplication and division with the pipelined version of .MIPS processor because such processor was not available in the market till the end of year 2007. As an alternate to this come up with the solution to implement floating point architecture of IEEE format in MIPS. Further more this project can use to enhance the simulator based approach by integrating some hardware design for the new learner to gain a hands-on experience in hardware-software integration and achieve a better understanding of the MIPS processors. Pipelining, which is one of the primary concepts to speed up a microprocessor is emphasized throughout this project. Pipelining is fundamentally invisible for high level programming language user.