FPGA implementation of fir filter for F-OFDM Systems (T-0433) (MFN 6908)

Abstract

Three contexts have been identified for 5G Wireless Communication Standard. These include Enhanced Modile Broad Band (eMBB), mMTC (Massive Machine Type Communication) and Ultra Reliable Low Latency Communication (URLLC). In order to achieve practical solutions of these identified contexts different waveforms have been proposed. Filter Bank Multi Carrier (FBMC), Generalized Frequency Division Multiplexing (GFDM), Universal Filtered Multi- Carrier (UFMC), and Filtered-Orthogonal Frequency Division Multiplexing (f-OFDM) techniques are proposed for their suitability to 5G requirements. Both UFMC and f-OFDM show very good out of band emission characteristic. On one side f-OFDM provides solution of eMBB, UFMC is a strong candidate for mMTC and URLLC due to its suitability for short data lengths. Moreover, they share similar building blocks with different associated parameters. In addition to the acceptable performance study of hardware cost associated with implementation of a concept is very important. In both of these waveform, FIR filtering is a major processing block. Hence, this thesis is aimed at real time hardware implementation of a flexible hardware architecture related to filtering part of UFMC and Filtered-OFDM transmitter. In this regard, first of all golden reference modes in C++ (Matlab) are created. Keeping into consideration the different filters associated with UFMC and f-OFDM, a flexible solution is then presented. Finally, the hardware design of presented model is modelled in Verilog HDL, which is then synthesized and implemented on FPGA.