Development of MIL-STD-1553 Data Bus Transceiver on FPGA (P-0318) (MFN 6823)

Abstract

This thesis discusses the development of MIL-STD-l 553 bus transceiver on FPGA. The US department of defense (DoD) defines military standards which give characteristics of different types of protocols and data buses. MIL-STD-1553 is a military avionics protocol which was defined by US Navy in 1973 which gives electrical, mechanical and functional characteristics of a serial data bus. Historically the commercial avionics designers have preferred other data bus protocols for their systems but now MIL-STD-1553 has become predominant and widely accepted standard for military platform integration. Initially this protocol was intended to be used in military avionics application but now it is widely used in weapon systems, ground vehicles, space stations and civil aerospace. The HI- 6110 is a CMOS integrated circuit designing the MIL-STD-1553 protocol between a host processor and a dual redundant MIL-STD-1553 data bus. The architecture of 1553 is implemented on a single chip HI-6110. This IC is mostly imported for its local industrial application. In the proposed system, MIL-STD-1553 protocol is implemented on FPGA. This system is specially developed on FPGA for local applications. FPGA will give immediate solution to the industry requirements. As FPGA is reprogrammable device so it also provides flexibility in programming and hardware design.