Variable Data Rate Bit Synchronizer (P-0321) (MFN 6820)

Abstract

Bit synchronization is very important operation III digital communications which is performed after the analog demodulation. In case of airborne telemetry systems, an aerial platform transmits data for post flight analysis, the data is corrupted by noise in the transmission medium. Analog front end at the receiver of the ground station, transfers the distorted peM data stream into bit synchronizer for optimal reconstruction of transmitted data and construction of a clock signal for synchronization to extract useful information. FPGA Based solution, has been proposed to meet the requirement of the user, achieve the data rate up-to lOMbps. A digital signal processing algorithm for bit synchronization has been implemented on Spartan-S, FPGA. The proposed model has a single channel input, supports one type of signal format NRZ-L. It offers data rate up-to lOMbps. It produces two outputs the reconstructed data and a synchronized clock.