Abstract:
Many wireless vision sensor networks (WVSNs) applications are characterized to have a low duty cycling. An individual wireless vision senor node (VSN) in WVSN is required to complete the tasks as quickly as possible. The execution of the tasks can be speeded up by exploiting the inherited parallelism in the tasks by using a hardware platform such as field-programmable gate array (FPGA). Traditionally, SRAM FPGAs are considered to be inefficient for duty cycled applications. This paper presents a low-complexity, energyefficient, and reconfigurable VSN architecture based on SRAM FPGA using a design matrix, which includes tasks’ partitioning, a low-complexity background subtraction, bilevel coding, and duty cycling. The proposed VSN, referred to as SENTIOF-CAM, has been implemented on a prototype board and energy values of different states are measured for three real applications. The comparison results with existing solutions show that the proposed architecture with SRAM FPGA can achieve energy reduction of up to a factor of 69 as compared with software VSN solutions and approximately similar energy values to that for the FLASH FPGA-based VSN solutions. The lifetime based on measured energy values shows that, for a sample period of 5 min, a 3.2-years lifetime can be achieved with a battery of 37.44-kJ energy. In addition, the proposed solution offers a generic architecture with a smaller design complexity on a hardware reconfigurable platform and offers easy adaptation for a number of applications.
