Design & Implementation of 3G Transmitter on FPGA (P-0044) (MFN 3531)

Abstract

In Pakistan, 3G technology is still in its introductory stages. 3G technology is much efficient as compared to 2G or 2.5G technology in terms of data rate, security and durability. Every mobile company in Pakistan has established their own 3G network but they are waiting for the license from Pakistan Telecom Authority (PTA) to launch their network. So it’s a perfect time to design and introduce a complete working prototype of 3G architecture. This project focuses on configurable and modular implementation of a complete 3G transmitter using W-CDMA protocol on Field Programmable Gate Arrays (FPGA) while a complete 3G transceiver prototype is also developed on MATLAB and Android platform using W-CDMA and cloud computing respectively. The different modules that are included in this project are: Cyclic Redundancy Check encoder (CRC), Convolutional encoder, One-Time Pad encryption, Block-Inter-leaver, Spreading, Real & Complex Scrambling, QPSK modulation, RRC filters, Interpolation, NCO and Band Pass filter. The implementation of this project is based on three software approaches and one hardware approach. Software approaches includes a complete simulation of 3G transmitter on Xilinx ISE (Integrated Simulation), MATLAB based simulation of 3G transceiver featuring audio/ video calls. The hardware approach of this project is based on FPGA. The mobile version of this project is based on Android platform for A/V transmission using cloud computing rather than W-CDMA. Both software and hardware implementation (except Android version which uses cloud computing) of this project are based on physical layer of UTRAN in W-CDMA architecture. In this project, all units described in W-CDMA standard, as proposed by 3GPP, are assembled and uniquely integrated together to provide a complete solution for communication using 3G protocol. In Xilinx ISE simulation, the 3G transmitter is been programmed in Verilog HDL without using any Intellectual Property (IP) Functions and by adding enhanced features of secure communication using cryptographic algorithm One Time Pad (OTP) encryption. This project provides a cryptographically secure 3G transmitter (and 3G transceiver in MATLAB and in Android version) which can be used in labs for learning of 3G W-CDMA architecture. The targeted FPGA component for the proposed design is SPARTAN III family of Xilinx.