Design & implementation of 3G receiver ( P-0050) (MFN 3538)

Abstract

3G technology has newly been introduced in Pakistan and is much more efficient as compared to older technologies of 2G or 2.5G in terms of data rate, security and reliability. Telecom companies of Pakistan have now established their own 3G networks but they are not currently issued the license from the Pakistan Telecom Authority to launch their networks. So this is the most suitable time to design and introduce a complete working prototype of 3G architecture. This project is based on the design and implementation of a 3G receiver using WCDMA protocol. The goal of this project is to receive the data securely using the cryptographic algorithm ONE TIME PAD at L1 layer in multimode environment. Both the sender and receiver will share a common key that may be changed by any of the two by mutual desire. Further we have implemented the complex De-Scrambling technique in our proposed design to uniquely identify different user packets received within the same bandwidth. This data travel is configurable where we can bring run time changes in our input. Our project includes the unique integration of the following modules without the use of inbuilt IP functions of Xilinx: Multi user detector, Multipath estimator, Decimator, De-Scrambler, De-Spreader, Channel estimator, De-Interleaver, One time pad, Convolutional decoder, Viterbi decoder and CRC (Cyclic Redundancy Checker)decoder. The FPGA tool that we have used for this purpose is SPARTAN III family of Xilinx ISE.