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Simulation of 8-bit Microprocessor (Controller and Random Access Memory)

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dc.contributor.author Shamaila Masood
dc.date.accessioned 2017-08-15T06:20:31Z
dc.date.available 2017-08-15T06:20:31Z
dc.date.issued 2002
dc.identifier.uri http://hdl.handle.net/123456789/4437
dc.description.abstract From the modest beginning in early 1984 at Gateway Design Automation, the Verilog hardware description language has become an industry standard as a result of extensive use in the design of integrated circuit chips and digital systems. Verilog came into being as a proprietary language supported by a simulation environment that was the first support mixed-level design representations comprising switches, gates, RTL, and high levels of abstractions of digital circuits. This project is my first experience of digital designing. This is an accumulator-based microprocessor. First, the detailed architecture was designed, and then depending on that architecture Verilog coding was done. Although Memory based Microprocessors are better than Accumulator based, but as I was totally new to Digital Designs in Veri log, I preferred Accumulator based. It can support II instruction of ALU, 3 instructions of AGU and 3 instruction pipeline stages. All the instructions were tested and waveforms were generated. The report discusses all the phases of project. en_US
dc.language.iso en en_US
dc.publisher Bahria University Islamabad Campus en_US
dc.relation.ispartofseries BS (CS);P-847
dc.subject Computer Sciences. en_US
dc.title Simulation of 8-bit Microprocessor (Controller and Random Access Memory) en_US
dc.type Project Reports en_US


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