Design and Implementation of Eathernet IP core using FPGA (P-0062) (MFN 2098)

Abstract

In this project, we have implement the transmitter and receiver code of Ethernet in verilog. In transmitter stage, we have gone through 5 stages. Getting input from the user, then calculating CRC,then managing the frame format and in the end applying Manchester coding and then transmitted the result of Manchester coding to Receiver. In receiver stage, the whole process is done in reverse order. Input is first gone through anti-manchester coding,then managing the frame format,the calculating CRC and then the output.