Simulation and FPGA Implementation of WCDMA Transceiver (P-0071) (MFN 2118)

Abstract

The third generation cellar (3G) system will seamlessly integrate a wide variety of services such as high speed internet access, video conferencing and multimedia application as well as voice signals. The main objective of this project is to develop a transmitter and receiver (transceiver) prototype of 3rd Code Division Multiple Access (CDMA) system, using field programmable gate array (FPGA) technology. This project is developed upon the basis of wideband code division multiple access (WCDMA) technology which is a widely accepted 3G interface based on direct sequence (DS) CDMA technology. The Verilog hardware description language (Verilog HDL) is used to develop the prototype for an uplink WCDMA system. The first part of the report relates to the theoretical background behind multiple access techniques and an overview is made of digital signal processing components inside the 3G transceiver. In the second part of the report, the basic development of Verilog HDL for uplink transmitter is described. Finally, this report summarizes the project by describing the general theory for the uplink WCDMA system and basic method used in Verilog HDL to develop the prototype. Some recommendations for the future work are also made.