Performance Characterization of Evoapproxlib Circuits for Errortolerant Computing

Abstract

The overall performance characterization of the approximate arithmetic circuits from the EvoApproxLib library is presented and its suitability for error-tolerant computing applications is discussed. EvoApproxLib contains a variety of evolutionarily synthesized approximate adders and multipliers of unique accuracy-efficiency tradeoff. This work has systematically characterized six approximate circuits, namely three variants of the adder (AA-L1, AA-L2, AA-L3) and three variants of the multiplier (AML1, AM-L2, AM-L3), in terms of Mean Error Distance (MED), Worst-Case Error (WCE), circuit area, power consumption, and propagation delay. Then, the characterized circuits are tested on a representative error-tolerant image processing application, Sobel edge detection, to check the characterization against real application level quality metrics. A structured characterization methodology is suggested and applied. First, the performance parameters of each of the EvoApproxLib-inspired circuits are defined by behavioral modeling. Each circuit is categorized within the error-tolerance tiers in accordance with its MED and WCE metrics. An exact baseline of Sobel convolution algorithm is then built in Python and all the arithmetic operations are isolated for systematic circuit changes. The approximation circuits characterized are provided as behavioral models to the Sobel kernel to allow application-level validation of the characterization results. Seven different configurations, each representing a variation of exact and approximate arithmetic, are explored in a systematic Design Space Exploration (DSE). Evaluation of the image quality with the help of Peak Signal-to-Noise Ratio (PSNR) and Structural Similarity Index (SSIM) with an exact reference output. Experimental results show that the PSNR and SSIM of Configuration C1 – Level-1 Approximate Adder with Exact Multiplier are 45.48 dB and 0.9997, respectively, which means that the visual degradation is imperceptible. The approximation level progressively decreases the image quality, with the higher levels C6 (Level-3 for both adder and multiplier) getting only 3.07 dB PSNR. The proposed Sobel architecture is programmed in the Verilog HDL using Xilinx 7-series FPGA. FPGA synthesis estimates confirm that Configuration C1 delivers 10.9% reduction in LUT utilization, 10.5% improvement in critical path delay, and 12.4% reduction in dynamic power consumption relative to the exact baseline. The benefits grow as the approximation level increases to 38.1% LUT reduction at Level-3, but with a degradation in image quality that is unacceptable. This thesis is the result of these conclusions, which indicate the possibility of significant hardware efficiency improvements in Sobel edge detection with minimal perceptual impact in the case of careful selection of level-1 approximate arithmetic. The proposed methodology, which is based on arithmetic modularization, behavioral approximation modeling, systematic DSE, evaluation of quality metrics and FPGA synthesis, offers an extensible and re-usable framework for approximate hardware design with quality constraints for error-resilient image processing applications.