Design of An Ultra-Low-Power Bluetooth Low-Energy Receiver Front end Building Blocks

Abstract

This research presents the design and optimization of a 2.4 GHz inductor-less, ultralow-power radio frequency (RF) front-end tailored for Internet of Things (IoT) applications, featuring a Gilbert double-balanced mixer, a low-noise amplifier (LNA), and a cross-coupled LC voltage-controlled oscillator (VCO). The growing adoption of IoT technologies, including Bluetooth Low Energy (BLE) and ZigBee, has heightened the demand for efficient, compact, and low-power RF circuits to extend battery life and reduce system costs. Implemented in a 65-nm CMOS process, these designs prioritize power efficiency, compactness, and performance. The proposed VCO employs a cross-coupled LC topology integrated with a D flip-flop frequency divider to achieve ultra-low-power consumption and excellent phase noise performance. Consuming only 0.47 mW, the VCO delivers a low phase noise of −118.36 dBc/Hz at a 1 MHz offset frequency. The VCO and frequency divider system operates with a total power consumption of just 2.02 mW and occupies an active chip area of 0.47 mm², demonstrating its suitability for system-on-chip (SoC) integration. The inductor-less Gilbert double-balanced mixer employs advanced current reuse techniques to enhance efficiency, achieving a high conversion gain of 17.38 dB, a noise figure of 7.34 dB, and substantial RF-to-IF and RF-to-LO isolation values of - 43.147 dB and -86.019 dB, respectively. It exhibits excellent linearity with an input thirdorder intercept point (IIP3) of -10.0 dBm and a 1 dB compression point of -2.57 dBm. The mixer consumes only 2.3 mW of power and occupies an ultra-compact chip area of 0.01007055 mm², making it ideal for space-constrained applications. Complementing the mixer and VCO, the LNA improves overall receiver performance by ensuring high signal sensitivity and low noise. Operating at 2.4 GHz, the LNA achieves a high gain of 28.059 dB, an input reflection coefficient of -13.5 dB for optimal impedance matching, and a low noise figure of 4.2 dB to minimize signal degradation. The LNA’s input third-order intercept point (IIP3) of -10.45 dBm ensures robust linearity, allowing it to handle large signals without distortion, further enhancing signal integrity. The chip's active area, including the pads, is only 0.00504 mm2. Together, these components address the critical design considerations for RF receivers, such as power efficiency, compactness, noise performance, and linearity. The designs’ minimal power consumption, compact chip areas, and superior performance metrics make them well-suited for BLE and ZigBee transceivers, particularly in applications demanding low cost and long battery life. By eliminating inductors, the designs reduce manufacturing complexity and chip size while enhancing scalability for future technologies. The combination of low power, high performance, and integration flexibility positions these components as strong candidates for modern IoT applications. This research contributes to the advancement of ultra-low-power RFIC solutions, meeting the growing demand for efficient and cost-effective receivers in the rapidly expanding IoT ecosystem. The thesis presents an ultra-low-power receiver frontend design using Cadence Virtuoso and CMOS 65-nm technology, including schematics, pre-layouts, and post-layouts.