ULP Power Amplifier Using 65nm CMOS Technology

Abstract

Power amplifier (PA) is the most power-hungry component of RF transceiver, portraying design issues. These include insufficient connectivity, power distribution, bandwidth, linearity and efficiency parameters that did not match system requirements. The primary challenge in a PA design is achieving higher efficiency while maintaining linearity over a bandwidth with wide range of output power levels. The power-added efficiency (PAE) is a figure-of-merit (FoM) that indicates how well the PA transforms DC power to RF power. Designers have raised concerns about PA in the front end of wireless radios because of the system's significant power consumption. There has been a lot of study on PA methods for optimizing PA efficiency. It is a challenging measure in the design of PAs for various low-power IEEE 802 wireless standards. The result to this study's primary concern and problem is this issue, that presents the design and optimization of two ultra-low power (ULP) PA architectures using 65-nm CMOS technology. The first part of the dissertation is ULP Doherty PA (DPA) architecture with fixed interstage capacitances. The main amplifier and the peaking amplifier have been designed and optimized with power divider & combiner models using equivalent lumped parameters. Due to 40 MHz narrowband communication (2.4 – 2.44 GHz ISM band), it offers fixed capacitances before the input-impedance stages, for a perfect impedance matching at both stages. The novel design shows 2.1mW ultra-low DC power consumption, 29.2% PAE, and 4 dBm P1-dB compression point. The post-layout simulations show an extremely high gain of 10.14 dB, very low input-insertion loss of - 11.9 dB, very strong drive current capability of 547µA & 663µA for main & peaking PAs respectively. Impedance matching is acquired to achieve the desired harmonic suppression at the output of DPA design. the consequences are all in comparison to state-of-the-art PA architectures for ZigBee and similar devices under short-range and low-power IEEE 802.15.4 WPAN standards. The second part of dissertation is class-F architecture with ET supply biasing to increase efficiency of overall PA design. The ET consists of a preamplifier before the envelope detector (ED) in a cascaded linear model, to increase efficiency and to reduce DC power consumption. The gate-to-drain feedback in the PA's two cascode cells, terminated as class-F, helps to improve linearity and reduce harmonic content in the input signal. The novel design meets the requirements of the IEEE 802.11ah standard for long-range low power WLAN by using a DC power consumption of 3.75mW, a PAE of 37.1%, and an operating frequency in the unlicensed 915-931 MHz band in the United States. The chip layout size is reduced to just 0.13mm2 by the ET inductor-less supply bias design.