Resource Optimize FPGA Implementation of Sonar System

Abstract

Field Programmable Gate Array (FPGA) is an efficient and compact tool for fast processing and computations of signals. In this project, we explore the capabilities of Sonar system implemented on FPGA, addressing the processing time to be minimized. Sonar technology is crucial for underwater target recognition, detection and also for other liabilities like, checking and measuring the underwater crimes. Typically, Sonar system rely on hydrophones for reliable processing. In this project, we are implementing the 6-channel linear array beamforming on FPGA. From each channel, data of 2048 samples were fed into the model for processing. The process begins with the application of a Fast Fourier Transform of the input data. The resulting FFT data is then subjected to beamforming, where desired frequency bins of the FFT result are multiplied by restored coefficients in a ROM. Finally, we take the Inverse Fast Fourier Transform to take the signal back into its original shape. We analyze the results by comparing it with the Matlab fix model benchmark. Our primary objective is the implementation of this linear beamforming on FPGA utilizing minimum Hardware resources. The system successfully meets the stringent requirement of processing the entire algorithm in under 2 milliseconds. The implementation was carried out using the Verilog hardware description language, ensuring an optimized and reliable solution for real-time sonar signal processing.