RISC-V Based Superscalar Processor

Abstract

In response to the growing number of digital products in the market, there is an increasing demand for powerful and highly adaptable processors. This demand is met by the stable and flexible open-sourced RISC-V instruction set architecture, which is gaining popularity across various applications and research domains. In Recent Years RISC-V Processors has gained significant attention as an Open-Source Instruction set Architecture. The existing RISC-V processors have limitations in terms of instruction throughput and Performance which limit their ability to achieve high performance in complex applications to overcome the problem of lack of support for superscalar instruction this thesis presents the design for a dual-issue superscalar RISC-V processor showcasing dynamic execution capabilities. The superscalar processor is extended with (ILP) Instruction Level Parallelism and Out of Order Execution to improve overall performance. Including implementation of branch prediction and Pipelining. Facilitating speculative execution with multiple ALUs, the processor optimizes the flow of data in the instruction dispatch and commit stages, aiming for increased efficiency in instruction throughput.