Design and Implementation of a Pipelined RISC-V Processor

Abstract

The goal of this research article is to enhance the processor’s throughput, latency, efficiency, and overall performance through the design and implementation of a pipe lined RISC-v processor. The project uses pipelining in an effort to get a better result. Pipe lining is a processor design approach that divides instruction execution into smaller, more closely spaced phases in order to maximize execution efciency.By using this method, the processor can work on several instructions at once, improving throughput and overall speed. The research strategy entailed examining the operation of the 32-bit program counter, fetcher, decoder, ALU, executer, and RISC-v processor. During the design stage, the instruction is fetched first, and decoded, and its function is ascertained. Following this, the instruction’s specified operation is carried out by the execution block, and memory is accessed to read or write data.The final step involves storing the operation’s outcome in the register fle. To store interim results and guarantee that they are executed one after the other during the implementation phase, pipe registers are added in between phases. The control unit assures correct execution, handles threats, and controls the flow of instructions via the pipeline. Subsequently, the processor’s correctness and performance are confrmed using simulation and verifcation methodologies. Processor efciency is assessed using performance indicators like throughput and clock cycles per instruction (CPI). Through the simultaneous execution of several instructions, the developed pipe lined RISC-v processor delivers better instruction throughput. The average number of clock cycles needed for each instruction will be lowered by the staged pipe lined design, improving processor performance and execution speed.