Abstract:
The performance of the digital communication links is partly dependent on the underlying digital modulation scheme. In presence of the time varying channel, the digital communication links with adjustable (run time reconfigurable) modulation schemes outperforms the conventional digital links with fixed modulation scheme in terms of data loss and energy efficiency. For performing different types of modulation we need different hardware devices. Industry requires a device that could perform various types of modulations over same hardware. So we had designed a reconfigurable modulator and demodulator using Verilog language on FPGA. Different Block RAM's and ROM's are used for storing data. When start gets high, mapper takes input data from a block RAM then shift them to a new register according to the selected modulation type and after addition generates a ROM address that maps real (1) and (Q) values. At demodulating end, these values are received after an addition of noise in term of Yi and Yq. Original values are stored in ROM's as Xi and Xq. Demapper runs in a finite state machine, these values are fetched and are transferred to process state and new value is formed. Then Minimum distance finder block finds the minimum distance value between various distances according to selected modulation type and clearing tail state is introduced to recover stalled values. Then LLR is generated in next state and if LLR is positive then output bit is 1 otherwise output bit is 0. Number of Output bits equals the selected modulation type selected. Whole algorithm works in pipeline to make it faster and efficient. In this way, bits send by mapper are demapped by demapper. Algorithm is designed to perform modulations for BPSK, QPSK, 8PSK, 16QAM, 32QAM, 64QAM, 128QAM, 256QAM. All the Simulations are performed on ISE Design suite by using test bench.
