Hardware Implementation of Grain-128 Cryptographic on FPGA

Abstract

With the rapid advancement of digital communication, securing the transmission of data has become a crucial concern. Encryption, a process of cryptography, is commonly used to ensure data privacy and prevent unauthorized access. In many cases, encryption is necessary when communicating between individuals or interrelated devices, such as in the Internet of Things (IoT) and RFID tags. As attackers continue to develop more sophisticated methods, it is essential to choose the most secure method of encryption. In an effort to establish standardized lightweight cryptography algorithms for devices with limited hardware resources, the National Institute of Standards and Technology (NIST) embarked on the Lightweight Cryptography (LWC) project. Following two rounds of evaluations, the NIST recently revealed the chosen finalists for this project in 2021. Among these fnalists, the Grain Family of Stream ciphers was also selected by the NIST. Then there is a choice of whether to use software implementation of the encryption algorithm or the hardware implementation. Software implementation of encryption algorithms is widely used but it has certain drawbacks, such as slow processing speed and long development cycles. As a result, hardware implementation is preferred. We have chosen FPGA because it gives more flexibility in terms of hardware designing since it is re-configurable. This final year project addresses the implementation, analysis and hardware resource utilization reporting on Xilinx FPGA part Spartan 7 family of devices.