Abstract:
Innovating information security applications including the Internet of things, wireless sensor networks, cloud computing, and radio frequency identification frequently use asymmetric cryptographic methods. Elliptic curve cryptography (ECC), a well-known asymmetric cryptographic technique, offers a secure environment for data exchange in resource-constrained embedded systems. The lack of uniqueness in point addition and point double equations makes ECC algorithms vulnerable to simple power analysis attacks. Unified cryptoprocessors like the binary Edward curve (BEC), binary huff curve (BHC), and Hessian curve (HC) offer resistance against simple power analysis. BEC is preferred over HC because it can achieve better throughput while utilizing fewer hardware resources, whereas BHC requires more hardware resources due to its complex computation. In this dissertation, we proposed a crypto accelerator BEC while requiring fewer hardware resources for the point multiplication architecture over GF(2m). The proposed crypto accelerator is designed to provide efficient hardware utilization. A Montgomery radix 4 multiplier is proposed as a solution for this. The projective coordinate Montgomery ladder algorithm (Lopez-Dahab) was employed to calculate the scalar multiplication. Effective scheduling of a two-stage pipeline architecture has been done to increase throughput. Finally, utilizing the Xilinx Vivado and ISE design software for various FPGA devices, the proposed architecture has been modeled in Verilog HDL. The findings obtained show how useful the proposed BEC accelerator is for resource-constrained embedded system applications that call for minimal area, low-power hardware and substantially greater speed. Keywords: Montgomery Radix 4 Multiplier, Binary Edward Curve, Scalar Multiplication, Elliptic Curve Cryptography, FPGA
