FPGA Implemention of Time Efcient Deinterleaving Algorithm

Abstract

In this work, a new deinterleaving algorithm that can be used as a part of an ESM system and its implementation by using an FPGA is studied. The function of the implemented algorithm is interpreting the complex electromagnetic military field in order to detect and determine different RADARs and their types by using incoming RADAR pulses and their PDWs.It is assumed that RADAR signals in the space are received clearly and the PDW of each pulse is generated as an input to the implemented algorithm system. Clustering analysis and a new interpreting process are used to deinterleave the RADAR pulses. In order to implement the algorithm, FPGA is used to achieve a faster and more efficient system. A comparison of the new algorithm and the previous deinterleaving studies is done. The simulation results are shown and discussed in detail.