FPGA Implementation of Lightweight Security Mechanism PRESENT-80

Abstract

The use of cryptographic techniques is crucial for securing resource-constrained devices and IoT networks that often have limited computing power and memory. However, due to their resource constraints, these devices are vulnerable to attacks such as side-channel attacks and tampering. Therefore, the use of lightweight standardized cipher models has gained attention as an effective solution for achieving security in these devices while minimizing the impact on their resources. By using these techniques, it is possible to address security problems such as confidentiality and integrity of data, secure bootstrapping, and secure communication. The PRESENT cipher is a symmetric-key block cipher that performs both encryption and decryption processes using a plaintext of 64 bits and a key size of 80 bits. The PRESENT cipher is a compact and efficient cipher that provides strong security for lightweight applications. The model design is performed by utilizing Verilog-HDL on the Xilinx Vivado software and is implemented on a SPARTAN-7 FPGA board. The performance analysis is carried out with respect to Slices, LUTs, and Flip-flops (FFs). The main purpose of the project is to provide a hardware-based implementation of the PRESENT cipher that improves the security and performance of resource-constrained applications such as embedded systems, IoT devices, and smart cards with minimal resource requirements. The project’s outcome can contribute to the development of lightweight security solutions that are efficient and secure while meeting the resource constraints of modern applications.