HARDWARE IMPLEMENTATION OF OVERLAP SAVE METHOD BASED FADING CHANNEL EMULATOR

Abstract

Wireless communication systems require extensive and thorough evaluations before field trials and actual deployment. Difficulty in real time testing makes it the least favourable option for field trials prior thorough evaluation in the laboratory. It is therefore, channel emulators are used to evaluate a waveform at real time data rate while emulating a channel. Among various channel emulation techniques, Overlap Save (OLS) method used along with inverse Fast Fourier Transform (IFFT) technique provides the best computational efficiency. Hardware solutions based upon OLS method based technique are not available. Implementation of OLS method based technique on FPGA is novel and provides high throughputs as compared to software solutions. In this thesis an FPGA based channel emulator is implemented which emulates a Rayleigh Fading channel along with Doppler effects. An OLS-based fading variates generator and a time domain OLS-based interpolator are implemented which shown reduction in complexity when compared with originally proposed OLS method. A high throughput of 34 Mega Samples per Second (MSPS) was targeted, keeping in view maximum sampling frequency in LTE which is 30.72MHz for a 20 MHz configuration. Design with minimal resources was implemented and required throughput was successfully achieved on Virtex-7 FPGA. Designing of system was done in such a way that system can be used with multiple antenna systems.