IMPLEMENTATION OF SIDE CHANNEL RESISTANT BINARY HUFF CURVES ON FPGA

Abstract

This thesis provides hardware architecture to perform point multiplication (PM) operation using recently proposed (in 2018) unified addition law of Binary Huff Curves (BHC) model of Elliptic Curve Cryptography (ECC). The most promising factors for performance contribution are Finite Field (FF) multiplication and inversion. In this regard, this work shows implementation of different FF multipliers, i.e., schoolbook, hybrid Karatsuba, 2-waykaratsuba, 3-way-toomcook and 4-way-toomcook and least-significant-digit-parallel, on Virtex 6 FPGA. To achieve FF inversion a square version of Itoh-Tsujii algorithm have been used. Thereafter, each implemented FF multiplier has been integrated in the proposed hardware architecture for PM to evaluate the area and latency tradeoffs. Finally, a performance comparison with state-of-the-art implementations has been provided.