LOW LATENCY MONTGOMERY MULTIPLIER FOR CRYPTOGRAPHIC APPLICATIONS

Abstract

In this modern era, protection of data is very important, to overcome these circumstances we can deploy different types of cryptographic algorithm such as VPNs, SSL and IPsec for securing our data from malicious attacks in many communication systems. Public channels are accessible to everyone, which is not safe for data and it cause high security risk. By having public-key cryptography, which provided secure communication between sender and receiver without need of sharing key at the beginning of communication. Public-key cryptographic systems such as ECC and RSA are implemented for different security services such as key exchange between sender, receiver and key distribution between different networks nodes and authentication protocols. Public Key (PK) cryptography is based on computationally intensive finite field arithmetic operations. Rivest, Shamir, Adelman (RSA) and Elliptic Curve Cryptography (ECC) are widely adopted public-key schemes. In these schemes, modular multiplication (MM) is the most critical operation. Usually, this operation is performed by integer multiplication (IM) followed by a Reduction Modulo M. However, the reduction step involves a long division operation that is expensive in terms of area, time and resources. Montgomery multiplication algorithm facilitates faster modular multiplication operation without the division operation. In this thesis, low latency hardware implementation of the Montgomery multiplier is proposed. Many interesting and novel optimization strategies are adopted in the proposed design. The proposed Montgomery multiplier is based on school-book multiplier, Karatsuba algorithm and fast adder’s techniques. The Karatsuba algorithm (KA) and School-book multiplier recommends cutting down the operands into smaller chunks while adders facilitate fast addition for large size operands. The proposed design is simulated, synthesized and implemented using Xilinx ISE Design Suite by targeting different Xilinx FPGA devices for different bit sizes (64-1024). The proposed design is evaluated on the basis of computational time, area consumption, and throughput. It outperforms the state of the art.