Software Pipelining Serial Assembly Optimizer for a VLIW Processor

Muhammad Salman

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dc.contributor.author	Muhammad Salman
dc.date.accessioned	2022-11-28T11:44:20Z
dc.date.available	2022-11-28T11:44:20Z
dc.date.issued	2001
dc.identifier.uri	http://hdl.handle.net/123456789/14087
dc.description	Supervised by Mr. Jahanzeb Ahmed	en_US
dc.description.abstract	We present a Serial Assemble Optimizer (SOA) for the Media Engine (ME-2), being developed in Communications Enabling Technology (CET). The SOA works 1n collaboration with the already coded module that takes the C code and converts it into the serial assembly, referred hereon as Front-end Serial Assembly Generator (FSAG). CET has only implemented a minimal functionality prototype of FSAG, whereas in actuality the GNU C compiler is being used as the serial code generator on the backend. Our project scope is the Serial Assembly Optimizer (SAO), which takes the serial code generated by the FSAG and makes use of advanced optimization techniques to generate a parallel, and optimized code. C Compiler	en_US
dc.language.iso	en	en_US
dc.publisher	Computer Sciences	en_US
dc.relation.ispartofseries	BS(CS);P-0695
dc.subject	Software Pipelining	en_US
dc.subject	Serial Assembly	en_US
dc.subject	Optimizer for a VLIW Processor	en_US
dc.title	Software Pipelining Serial Assembly Optimizer for a VLIW Processor	en_US
dc.type	Project Reports	en_US