DSpace Repository

Hashing in Hardware

Show simple item record

dc.contributor.author Shamaila Masood, 141022-036
dc.date.accessioned 2022-10-24T08:34:39Z
dc.date.available 2022-10-24T08:34:39Z
dc.date.issued 2004
dc.identifier.uri http://hdl.handle.net/123456789/13751
dc.description Supervised by Mr. Jahanzaib Ahmad en_US
dc.description.abstract Digi~al syst~m.s are highly complex. At their most detailed level, they may consist of millions of elements, e.g., transistors or logic gates. For many decades, logic schematics served as the lingua franca of logic design, but not any more. Today, hardware complexity has grown to such a degree that a schematic with logic gates is almost useless, as it shows only a web of connectivity and not the functionality of design. Since the 1970s, computer engineers and electrical engineers have moved toward hardware description languages (HDLs ). The most prominent HDLs in industry are Veri log and VHDL. Verilog is the top HDL used by over 10,000 designers at such hardware vendors as Sun Microsystems, Apple Computer and Motorola. Industrial designers prefer Verilog. The syntax ofVerilog is based on the C language, while the syntax of VHDL is based on Ada. A free Veri log simulator is available from SynaptiCAD, Inc. For Windows 95/NT, Windows 3.1 , Macintosh, SunOS and Linux platforms, they offer FREE versions of their VeriWeii product, which is available from http://www.syncad.com/ver _ down.htm. The free versions are the same as the industrial versions except they are restricted to a maximum of 1000 lines of HDL code. en_US
dc.language.iso en en_US
dc.publisher Computer Sciences en_US
dc.relation.ispartofseries MS(CS);T-1164
dc.subject Hashing en_US
dc.subject Hardware en_US
dc.title Hashing in Hardware en_US
dc.type MS Thesis en_US


Files in this item

This item appears in the following Collection(s)

Show simple item record

Search DSpace


Advanced Search

Browse

My Account