Design and Implementation of Ethernet Encryptor (P-0105) (MFN 3140)

Abstract

This project is to design and implement 128-bit Ethernet cryptographic process using FPGA. .The goal of the project is to securely transmit data over transmission medium. The Administrator will have the right to change the key length and to change the mode of operations which provides more customization and flexibility at the user end. The design of this project includes AES (Encryption / Decryption), modes of operations i.e. OFB (Output Feedback), CFB (Cipher feedback), CTR (Counter Mode), along with key size of different lengths such as 128, 192, 256 bits. This project is implemented on Xilinx Virtex-4 FPGA device. The software part of the project is implemented in Verilog HDL, which is Hardware Description Language and synthesize using Xilinx ISE.