Crypto Graphic Processor Base on FPGA (P-0207) (MFN 2812)

Abstract

The project idea is about to design a cryptographic processor implementing AES as the algorithm for encryption/decryption processing. AES is selected from other cryptographic standards because it is stronger and faster and more reliable than DES and triple DES algorithms. AES is the first publicly accessible and open cipher algorithm that is approved by the NSA for top information. This algorithmic core is designed to receive data from an off-chip source, and encrypt/decrypt the data using the AES encryption standard. Finally it sends the data back off chip via serial interface. The serial interface allows communication between the system and a PC for sending data and a key .The heart of this design is a field programmable gate array (FPGA) which is reprogrammable and reconfigurable and offers high complex logical capacity. FPGA offers a promising, robust, reliable alternative for the implementation of the processors through use of IP cores and algorithms in field of FPGA. This product has applications in both the government as well as public sectors .In the government sector; armed forces are already using cryptographic processors to provide link security. However those devices are not configuring security parameters and therefore they may be susceptible to attacks. This product not only will not only meet the security requirements but it will also open the doors to add further improvements as and when required. In public sector our product can be utilized in finance industry (banking sector), telecommunication industry (mobile devices), networking services (Voice over Internet Protocol), etc for security purposes globally.