Abstract:
Hardware-based implementations of stream ciphers and ring-learning with error lattice-based post-quantum cryptography (RLWE-LB-PQC) ciphers are requirements of resource constraint and modern computing environments with extensive computing and security requirements respectively. Stream ciphers, speedy and simple are for serial communication, whereas privacy persevering services based on RLWE-LB-PQC ciphers will replace currently in practice public key cryptographic services soon, because these computationally secure crypto-systems will not resist against the quantum computing attacks. Thesis reviews the efficiencies of stream hardware ciphers Grain (80 & 128), Trivium, and MICKEY (80 &128 2.0) when loop unrolling is in equation as well as discusses the need of light weight and throughput/area efficient stream ciphers. Area consumption to achieve better throughput/area is bench-marked along with probing optimal implementations while designing high-performance stream ciphers. Our experimental results show loop-unrolling affects stream ciphers’ performance in a different way than technology library theoretical predictions. Our findings, implementation suggestions, and unrolled cipher designs aid hardware designers in making informed decisions. We study stream ciphers’ area-efficiency saturation and support our claim with pre-layout synthesis results on ASIC (65nm &130nm) and that of Xilinx FPGA platform for stream ciphers. We also study why RLE-LB-PQC polynomial multiplication (an important and only function of RLWE-LB-PQC ciphers with acceleration potential) implementations cannot be further accelerated without significant design changes. It is because loops are found fully unrolled in selected polynomial multiplication implementations without changing original designs significantly. Which is somewhat comparable to loops in MICKEY as we apply somewhat similar technique learnt from stream ciphers’ loop unrolling? We review the potential of loop-unrolling (Throughput/area) in polynomial multiplication using Viv ado and FPGA Artix-7. Block ciphers are not covered because acceleration in block cipher is achieved by simple replication of computational blocks. And this is beyond our selected area i.e. accelerating without significant hardware changes
