Abstract:
This thesis deals with a top-down design methodology of a connectionist neural Network-based upon parametric Verilog HDL description. To come off early in the design process, a high regular architecture was achieved. Then, the Verilog HDL parametric description of the network was realized. The description is the building block of the architecture and has advantages such as generic, flexible and could be easily modified as the dictates of user requirements. Hardware programming of the connectionist neural network becomes very interesting due to re-programmability features of application tools such as FPGA circuits. More precisely, the Verilog HDL based synthesis tools have become very popular due to the need-driven approach of today, to get a correctly working system in the first place. Moreover, the system has to be technology independent design having the capability of design reusability, the ability to experiment with several alternatives of the design, and economic factors such as time to market. To this aim, the digital implementation of Feed-Forward Connectionist Network is proposed in this thesis using Verilog HDL synthesis tools. A new design methodology of ANNs based upon Verilog HDL synthesis of the network will be applied. The proposed architecture can be used in different Machine Learning applications such as Classification, Controls, Estimation, and Prediction, etc. The proposed methodology, however, is mainly focused on the Classification application and its illustration while using the FPGA as a tool. Further, the design is capable enough to be modified based on the dictates of the user requirements for any specific project proposed to achieve the results in the used cases in hand. The implementation of Feed-Forward Connectionist Network could then be driven from this as a take-off platform for subsequent development carefully tailored to meet the user demands.
